The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of performing a multi-chip redundancy operation by respectively storing self-chip redundancy information and other chip redundancy information in a plurality of semiconductor chips.
Many semiconductor chips include a redundancy block (or redundancy region) used to replace (or substitute) defective memory cells identified in a larger memory block. Memory cell (or memory portion) replacement within the redundancy block is conventionally accomplished by first receiving an externally supplied address corresponding to the defective memory cell and thereafter configuring a signal path to replace the defective memory cell by such methods as laser fuse cutting, etc. In this manner, a semiconductor chip having defective memory cells may effectively be repaired. Once repaired, the semiconductor chip is operated by recognizing an applied address in relation to stored addresses associated with memory cells in the redundancy block. However, when the number of defective memory cells exceeds the number of replacement memory cells provided by the redundancy block, the semiconductor chip can not be repaired.
Many conventional subsystems and integrated circuit architectures (e.g., a multi-chip semiconductor device) include a plurality of semiconductor chips. Each one of the plurality of semiconductor chips may incorporate the foregoing effective memory cell repair capability. This possibility raises an interesting capabilities question. For example, when a first conventional semiconductor chip in a plurality of conventional semiconductor chips includes more defective memory cells than its constituent redundancy block can repair, it must be replaced within the multi-chip device, despite the fact that some other semiconductor chip in the device has unused capability within it constituent redundancy block sufficient to repair the first semiconductor chip.